From RTL to silicon — building a custom chip for $15K with open-source tools.
After the bug that almost killed the chip, every check passed and we did not trust them anymore. Here is the multi-week systematic audit we built to interrogate every category of pre-tape-out signoff before submitting Kyttar to the MPW shuttle.
The standard chip design convention runs static timing analysis at three PVT corners. For an asynchronous bundled-data design, three corners is not enough. The corners that nobody checks are exactly where async timing breaks.
Our first IDDQ simulation said the slow corner leaked more than the fast corner. That is physically impossible. The numerical artifact hiding the truth was a single line in the SPICE convergence options.
A pre-tapeout audit uncovered that 98.5% of our wire delays were zero. Every check in the flow said clean. The bug was in the checking infrastructure itself, hiding a functional failure waiting to happen on silicon.
What happens when the standard cell library does not have the cells you need. Drawing custom SKY130 cells in Magic, simulating with ngspice, and why we ultimately went a different direction.
SDC is built around clocks. Every constraint references a clock. So what do you do when there is no clock? Virtual clocks, per-handshake domains, and false paths on everything the tools should not touch.
How we use Yosys to synthesize a fully asynchronous processor. C-elements from standard cells, delay chains that survive optimization, and latches that actually work.
How a single config file and one command replaces the scripts, Makefiles, and tribal knowledge that every chip team dreads. LibreLane, Nix containers, ChipFoundry's cf wrapper, and OpenFrame.
Every tool in our RTL-to-silicon flow. How we're building a custom asynchronous processor for $15K using free tools, the SKY130 PDK, and ChipFoundry's ChipIgnite platform.